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avalanche photodiode bias controller and wide range (5 na to 5 ma) current monitor ADL5317 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features accurately sets avalanche photodiode (apd) bias voltage wide bias range from 6 v to 75 v 3 v-compatible control interface monitors photodiode current (5:1 ratio) over six decades linearity 0.25% from 10 na to 1 ma, 0.5% from 5 na to 5 ma overcurrent protection and overtemperature shutdown miniature 16-lead chip scale package (lfcsp 3 mm 3 mm) applications optical power monitoring and biasing in apd systems wide dynamic range voltage sourcing and current monitoring in high voltage systems functional block diagram overcurrent protection thermal protection falt vset vplv vphv vphv vclh gard vapd i apd current mirror 5:1 30 v set i apd 5 ADL5317 r 29 r 05456-001 comm 16 comm 15 comm 14 comm 13 13 1 2 3 4 5 6 7 8 ipdm 11 12 nc 10 nc 9 gard figure 1. general description the ADL5317 is a high voltage, wide dynamic range, biasing and current monitoring device optimized for use with avalanche photodiodes. when used with a stable high voltage supply (up to 80 v), the bias voltage at the vapd pin can be varied from 6 v to 75 v using the 3 v-compatible vset pin. the current sourced from the vapd pin over a range of 5 na to 5 ma is accurately mirrored with an attenuation of 5 and sourced from the ipdm monitor output. in a typical application, the monitor output drives a current input logarithmic amplifier to produce an output representing the optical power incident upon the photodiode. the photodiode anode can be connected to a high speed transimpedance amplifier for the extraction of the data stream. a signal of 0.2 v to 2.5 v with respect to ground applied at the vset pin is amplified by a fixed gain of 30 to produce the 6 v to 75 v bias at pin vapd. the accuracy of the bias control interface of the ADL5317 allows for straightforward calibration, thereby maintaining a constant avalanche multiplication factor of the photodiode over temperature. the current monitor output, ipdm, maintains its high linearity vs. photodiode current over the full range of apd bias voltage. the current ratio of 5:1 remains constant as v set and v phv are varied. the ADL5317 also offers a supply tracking mode compatible with adjustable high voltage supplies. the vapd pin accurately follows 2.0 v below the vphv supply pin when vset is tied to a voltage from 3.0 v to 5.5 v (or higher with a current limiting resistor), and the vclh pin is open. protection from excessive input current at vapd as well as excessive die temperature is provided. the voltage at vapd falls rapidly from its setpoint when the input current exceeds 18 ma nominally. a die temperature in excess of 140c will cause the bias controller and monitor to shut down until the temperature falls below 120c. either overstress condition will trigger a logic low at the falt pin, an open collector output loaded by an external pull-up to an appropriate logic supply (1 ma max). the ADL5317 is available in a 16-lead lfcsp package and is specified for operation from ?40c to +85c.
ADL5317 rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 typical performance characteristics ............................................. 6 theory of operation ........................................................................ 9 bias control interface .................................................................. 9 gard interface ............................................................................ 9 vclh interface .......................................................................... 10 noise performance ..................................................................... 10 response time ............................................................................ 10 device protection ....................................................................... 10 applications ..................................................................................... 11 supply tracking mode ............................................................... 11 translinear log amp interfacing ............................................. 11 characterization methods ........................................................ 12 evaluation board ............................................................................ 14 outline dimensions ....................................................................... 16 ordering guide .......................................................................... 16 revision history 7/05revision 0: initial version
ADL5317 rev. 0 | page 3 of 16 specifications v phv = 78 v, v plv = 5 v, v apd = 60 v, i apd = 5 a, t a = 25 c, unless otherwise noted. table 1. parameter min typ max unit conditions current monitor output ipdm (pin 11 ) current gain from vapd to ipdm 0.198 0.200 0.202 a/a t a = 25 c 0.193 0.207 ?40 c < t a < +85 c 0.25 1.6 % 10 na < i apd < 1 ma nonlinearity 0.5 3.0 % 5 na < i apd < 5 ma 2 khz i apd = 5 na, v phv = 60 v, v apd = 30 v small-signal bandwidth 2 mhz i apd = 5 a, v phv = 60 v, v apd = 30 v wideband noise at ipdm 10 na i apd = 5 a, c grd = 2 nf, bw = 10 mhz, v phv = 40 v, v apd = 30 v 0 v plv v v apd > 3 v plv output voltage range 0 v apd / 3 v v apd < 3 v plv apd bias control vset (pin 2), vapd (pin 8) 6 v phv ? 1.5 v 10 v < v phv < 41 v v phv ? 35 v phv ? 1.5 v 41 v < v phv < 76.5 v specified v apd voltage operating range v phv ? 35 75 v 76.5 v < v phv < 80 v vapd to gard offset 3 mv specified input current range, i apd 5n 5m a flows from vapd pin vset to vapd incremental gain 29.7 30 30.3 v/v 0.2 v < v set < 2.5 v 1 vset input referred offset, 1 0.5 mv vset voltage range 0.2 5.5 v incremental input resistance at vset 100 m v set = 2.0 v input bias current at vset 0.3 a v set = 2.0 v, flows from vset pin 20 sec v set = 1.6 v to 2.4 v, c grd = 2 nf, v phv = 60 v, v apd = 30 v v apd settling time, 5% 100 sec v set = 2.4 v to 1.6 v, c grd = 2 nf, v phv = 60 v, v apd = 30 v v apd supply tracking offset (below v phv ) 1.90 2.0 2.15 v v set = 5.0 v, 10 v < v phv < 77 v overstress protection falt (pin 1) vapd current compliance limit 14 18 21 ma v set = 2.0 v, v apd deviation of 500 mv thermal shutdown trip point 140 c die temperature rising thermal hysteresis 20 c falt output low voltage 0.8 v fault condition, load current < 1 ma power supplies vphv (pin 4, pin 5), vplv (pin 3) low voltage supply 4 6 v vplv quiescent current 0.7 0.84 ma independent of i apd high voltage supply 10 80 v vphv quiescent current 2.3 2.9 ma i apd = 5 a, v apd = 60 v 3.6 4.5 ma i apd = 1 ma, v apd = 60 v 1 tested 1.5 v < v set < 2.5 v, guaranteed operation 0.2 v < v set < 2.5 v.
ADL5317 rev. 0 | page 4 of 16 absolute maximum ratings table 2. parameter rating supply voltage 80 v input current at vapd 25 ma internal power dissipation 615 mw ja (soldered exposed paddle) 65c/w maximum junction temperature 125c operating temperature range ?40c to +85c storage temperature range ?65c to +150c lead temperature range (soldering 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality.
ADL5317 rev. 0 | page 5 of 16 pin configuration and function descriptions pin 1 indicator 1falt 2vset 3vplv 4vphv 11 ipdm 12 nc 10 nc 9 gard 5 v p h v 6 v c l h 7 g a r d 8 v a p d 1 5 c o m m 1 6 c o m m 1 4 c o m m 1 3 c o m m top view (not to scale) ADL5317 nc = no connect 05456-002 figure 2. pin configuration table 3. pin function descriptions pin no. mnemonic description 1 falt open collector (active low) logic output. indicates an overcurrent or overtemperature condition. 2 vset apd bias voltage setting input. short to vplv for supply tracking mode. 3 vplv low voltage supply, 4 v to 6 v. 4, 5 vphv high voltage supply, 10 v to 80 v. 6 vclh can be shorted to vphv for extended linear operating range. no connect for supply tracking mode. 7, 9 gard guard pin tracks vapd pin and filters setpoi nt buffer noise (with external capacitor c grd to comm). optional shielding of vapd trace. capacitive load only. 8 vapd apd bias voltage output and current input. sources current only. 10, 12 nc optional shielding of ipdm trace. no connection to die. 11 ipdm photodiode monitor current output. sources cu rrent only. current at this node is equal to i apd /5. 13 to 16 comm analog ground.
ADL5317 rev. 0 | page 6 of 16 typical performance characteristics v phv = 78 v, v plv = 5 v, v apd = 60 v, i apd = 5 a, t a = 25 c, unless otherwise noted. 10m 2.0 100p ?2.0 1n 10m i apd (amperes) i pdm (amperes) i pdm linearity (%) 10n 100n 1 10 100 1m 1m 1.5 100 1.0 10 0.5 1 0 100n ?0.5 10n ?1.0 1n ?1.5 +25 c ?40 c +85 c +85 c +25 c ?40 c 05456-003 figure 3. i pdm linearity for multiple temperatures, normalized to i apd = 5 a, 25c 80 0 0 3.0 v set (v) v apd (v) 70 60 50 40 30 20 10 0.5 1.0 1.5 2.0 2.5 v phv = 45v, ?40 c v phv = 45v, +85 c v phv = 45v, +25 c v phv = 78v, +25 c v phv = 78v, ?40 c 05456-006 v phv = 78v, +85 c figure 4. v apd vs. v set for multiple temperatures, v phv = 78 v and v phv = 45 v, i apd = 5 a 2.150 1.850 09 0 v phv (v) v phv ? v apd (v) 2.125 2.100 2.075 2.050 2.025 2.000 1.975 1.950 1.925 1.900 1.875 10 20 30 40 50 60 70 80 ?40 c +25 c +85 c 05456-005 figure 5. v apd supply tracking offset vs. v phv for multiple temperatures 2.0 ?2.0 i apd (amperes) i pdm (amperes) i pdm linearity (%) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 10m 100p 1n 10m 10n 100n 1 10 100 1m 1m 100 10 1 100n 10n 1n 05456-004 v phv = 78v, v apd = 60v v phv = 45v, v apd = 32v v phv = 10v, v apd = 6v v phv = 78v, v apd = 60v v phv = 45v, v apd = 32v v phv = 10v, v apd = 6v figure 6. i pdm linearity for multiple values of v apd and v phv , normalized to i apd = 5 a, v phv =78 v, v apd = 60 v 31.0 29.0 0 3.0 v set (v) gain (v/v) 0.5 1.0 1.5 2.0 2.5 05456-007 30.8 30.6 30.4 30.2 30.0 29.8 29.6 29.4 29.2 v phv = 45v, +85 c v phv = 45v, +25 c v phv = 45v, ?40 c v phv = 78v, +85 c v phv = 78v, +25 c v phv = 78v, ?40 c figure 7. incremental gain from v set to v apd vs. v set for multiple temperatures, i apd = 5 a, v phv = 78 v and 45 v 70 0.030 0 ?0.040 1n 10m i apd (amperes) v apd (v) v apd variation (v) 10n 100n 1 10 100 1m 60 0.020 50 0.010 40 0 30 ?0.010 20 ?0.020 10 ?0.030 05456-008 78/60 +25 c 45/32 +25 c 10/6 +25 c 78/60 ?40 c 45/32 ?40 c 10/6 ?40 c 78/60 +85 c 45/32 +85 c 10/6 +85 c v phv = 78v, v apd = 60v; +85 c, +25 c, ?40 c v phv = 45v, v apd = 32v; +85 c, +25 c, ?40 c v phv = 10v, v apd = 6v; +85 c, +25 c, ?40 c figure 8. v apd vs. i apd for multiple temperatures and values of v phv and v apd
ADL5317 rev. 0 | page 7 of 16 3 ?3 1n 10m i apd (amperes) i pdm linearity (%) 10n 100n 1 10 100 1m 2 1 0 ?1 ?2 05456-010 +85 c +25 c ?40 c figure 9. i pdm linearity for multiple temperatures and devices v phv =75 v, v apd = 60 v, normalized to i apd = 5 a, 25c 100pa 1fa 1k 10m frequency (hz) (amperes rms/ hz) 05456-035 10k 100k 1m 10pa 1pa 100fa 10fa 500 a 500na 5ma 50na 5na 5 a 50 a figure 10. output current noise density vs. frequency for multiple values of i apd , c gard = 2 nf, v phv = 40 v, v apd = 30 v temperature ( c) v apd drift (mv) 05456-042 ?40 ?30 ?20 ?10 0 10 20 30 ?40 90 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 +3 sigma ?3 sigma average figure 11. temperature drift of v apd , 3 to either side of mean 3 ?3 1n 10m i apd (amperes) i pdm linearity (%) 10n 100n 1 10 100 1m 2 1 0 ?1 ?2 05456-011 +85 c +25 c ?40 c figure 12. i pdm linearity for multiple temperatures and devices v phv = 45 v, v apd = 32 v, normalized to i apd = 5 a, 25c (%) 05456-036 4.5 0 1n 1m i pdm (amperes) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 10n 100n 1 10 100 figure 13. output wideband current noise as a percentage of i pdm vs. i pdm , c gard = 2 nf, v phv = 40 v, v apd = 30 v, bw = 10 mhz 10 ?30 frequency (hz) normalized response (db) 05456-043 5 0 ?5 ?10 ?15 ?20 ?25 100m 10 100 1k 10k 100k 1m 10m 50 a 5na 50na 500na 5 a figure 14. small signal ac response from i apd to i pdm , for i apd in decades from 5 na to 50 a, v phv = 60 v, v apd = 30 v
ADL5317 rev. 0 | page 8 of 16 10m 1n 10n 0 400 time ( s) i pdm (amperes) 1m 100 10 1 100n 10n 50 100 150 200 250 300 350 05456-016 10 a to 100 a: t-rise = < 0.5 s, t-fall = < 0.5 s 100 a to 1ma: t-rise = < 0.5 s, t-fall = < 0.5 s 1 a to 10 a: t-rise = < 0.5 s, t-fall = < 0.5 s 100na to 1 a: t-rise = < 1 s, t-fall = < 1.5 s 10na to 100na: t-rise = < 10 s, t-fall = < 15 s 1na to 10na: t-rise = < 100 s, t-fall = < 150 s figure 15. pulse response from i apd to i pdm for i apd in decades from 5 na to 5 ma, v phv = 60 v, v apd = 30 v slope (v/v) (%) 05456-038 29.7 29.8 29.9 30.0 30.1 30.2 30.3 0 5 10 15 20 25 30 n = 2021 mean = 29.959 sd = 0.0316714 figure 16. distribution of incremental gain from v set to v apd for v set from 1.5 v to 2.4 v, i apd = 5 a 75 45 0 400 time ( s) v apd , voltage (v) 70 65 60 55 50 50 100 150 200 250 300 350 5na 50na 500na 50 a 500 a 5ma 5 a 05456-017 figure 17. pulse response from v set to v apd (v set pulsed 1.6 v to 2.4 v) for i apd in decades from 5 na to 5 ma, c gard = 2 nf, v phv = 60 v, v apd = 30 v i pdm /i apd (a/a) (%) 05456-039 0.1980 0.1985 0.1990 0.1995 0.2000 0.2005 0.2010 0.2015 0.2020 0 20 15 10 5 n = 2029 mean = 0.200035 sd = 0.000454209 figure 18. distribution of i pdm /i apd at v phv = 60 v, v set = 1.0 v, i apd = 50 a
ADL5317 rev. 0 | page 9 of 16 theory of operation the ADL5317 is designed to address the need for high voltage bias control and precision optical power monitoring in optical systems using avalanche photodiodes. it is optimized for use with the analog devices, inc. family of translinear logarithmic amplifiers that take advantage of the wide input current range of the ADL5317. this arrangement allows the anode of the photodiode to connect directly to a transimpedance amplifier for the extraction of the data stream without need for a separate optical power monitoring tap. figure 19 shows the basic connections for the ADL5317. 1 falt 2 v set 3 4 11 ipdm 12 nc 10 nc 9 gard 5 v p h v 6 v c l h 7 g a r d 8 v a p d 1 5 c o m m 1 6 c o m m 1 4 c o m m 1 3 c o m m ADL5317 falt vset vplv vphv mirror current output 0.01 f apd 1nf 1k i apd 0.1 f 0.01 f high voltage supply 0 low voltage supply 10k 0 0.01 f 0.1 f 05456-021 figure 19. basic connections at the heart of the ADL5317 is a precision attenuating current mirror with a voltage following characteristic that provides precision biasing at the monitor input. this architecture uses a jfet-input amplifier to drive the bipolar mirror and maintain stable v apd voltage, while offering very low leakage current at the vapd pin. the mirror attenuates the current sourced through vapd by a factor of 5 to limit power dissipation under high voltage operation and delivers the mirrored current to the ipdm monitor output pin. proprietary mirroring and cascoding techniques maintain the linearity vs. the input current and stability of the mirror ratio over a very wide range of supply and v apd voltages. bias control interface in the linear operating mode, the voltage at vapd is referenced to ground, and follows the simplified equation v apd = 30 v set gard is driven to the same potential as vapd for use in shielding the highly sensitive vapd pin from leakage currents. the gard and vapd pins are clamped to within approxi- mately 40 v below the vphv supply to prevent internal device breakdowns, and vapd is clamped to within a volt of gard. the vapd adjustment range for a given high voltage supply, vphv, is limited to approximately 33 v (or less, for v phv < 41 v). for example, vapd is specified from 40 v to 73.5 v for a 75 v supply, and 6 v (the minimum allowed) to 28.5 v for a 30 v supply. when vapd is driven to its lower clamp voltage via the vset pin, the mirror can continue to operate, but the vapd bias voltage no longer responds to incremental changes in v set . gard interface the gard pins primarily shield the vapd trace from leakage currents and filter noise from the bias control interface. gard is driven by the v set amplifier through a 20 k resistor. this resistor forms an rc network with an external capacitor from gard to ground that filters the thermal noise of the amplifiers feedback network and provides additional power supply rejection. the series components, r comp and c comp , shown in figure 20 , are necessary to ensure essential high frequency compensation at the vapd input pin over the full operating range of the ADL5317. v set amplifier gard c grd ADL5317 x30 05456-022 vapd c comp r comp 20k figure 20. filtering vapd using the gard interface the cutoff frequency of the gard interface for small signals and noise is defined by grd 3db c f = k 20 2 1 where: f 3db is the cutoff frequency of the low-pass filter formed by the on-board 20 k and c grd . c grd is the filter capacitor installed from gard to ground. a larger value for c grd (up to approximately 0.01 f) provides superior noise performance at the lowest input current levels, but also slows the response time to changes in v set . the pull-up of the v set amplifier is limited to approximately 2.5 ma, resulting in a slew limited region for large signals, followed by an rc decay for the final 700 mv. this decay corresponds to the above single-pole equation. the pull-down of the v set amplifier is largely resistive, equivalent to approximately 90 k in parallel with 70 a to ground.
ADL5317 rev. 0 | page 10 of 16 for small input currents, this pull-down must discharge not only c grd but also c comp at the vapd pin (through the gard and vapd diodes). the final 700 mv of settling for lower input currents is dominated by the input current discharge of c comp . for larger input currents, the v set amplifier pull-down discharges only c grd , since i apd is capable of discharging c comp quickly (see figure 17 ). any dc load on gard alters the gain from vset to vapd due to the 20 k source impedance. note that the load presented by a multimeter or oscilloscope probe is sufficient to alter the vset to vapd gain, and must be taken into account. the gard pin is internally clamped to approximately 40 v below vphv to prevent device breakdown, and vapd is clamped to within 1 v of gard. for this reason, any short- circuit to ground from gard or vapd must be avoided for vphv voltages above 36 v, or device damage results. vclh interface the voltage clamp high-side pin (vclh) is typically connected to vphv for linear operation of the vset interface and left open for supply tracking mode (see the supply tracking mode section for more details). the voltage at vclh represents a high-side clamp above which the v set amplifier output (and v apd ) is not allowed to rise. the voltage is internally set to a temperature stable 2.0 v below v phv through a 25 k resistor. when v set is pulled up to 3 v or higher and vclh is open, vapd follows 2.0 v below vphv as vphv is varied. this bypasses the linear vset interface for applications where an adjustable high voltage supply is preferred (see the applications section). the 25 k source resistance allows vclh to be shorted to vphv, removing the 2.0 v high-side clamp for extended linear operating range (up to v phv ? 1.5 v) in linear mode. vclh can be left open in linear mode if a fixed clamp point is desired. noise performance the noise performance for the ADL5317, defined as the rms noise current as a fraction of the output dc current, improves with increasing signal current. this partially results from the relationship between quiescent collector current and shot noise in bipolar transistors. at lower signal current levels, the noise contribution from the v set amplifier and other noise sources appearing at vapd dominate the noise behavior. filtering the vset interface noise through an external capacitor from gard to ground, as well as selecting optimal external compensation components on vapd, minimizes the amount of voltage noise at vapd that is converted to current noise at ipdm. response time the response time for changes in signal current is fundamentally a function of signal current, with small-signal bandwidth increasing roughly in proportion to signal current. the value of the exter- nal compensating capacitor on vapd strongly affects response time, although the value must be chosen to maintain stability and prevent noise peaking. response time for changes in v set voltage is primarily a function of the filter capacitance at the gard pin. see the gard interface section for further details. figure 15 and figure 17 show the response of the ADL5317 to pulsed input current and v set voltage, respectively. device protection thermal and overcurrent protection are provided with fault detection. the falt pin is an open collector logic output (active low) designed to assert when an overtemperature or overcurrent condition is detected. a pull-up resistor to an appropriate logic supply is required, and its value should be chosen such that no more than 1 ma output current is used when active. when the die temperature of the ADL5317 exceeds 140c (typical), the current mirror shuts down, causing the bias voltage at vapd to be pulled down, and falt asserts. falt remains asserted until the temperature falls below the trigger temperature minus the thermal hysteresis (20c typical), after which the mirror and biaser again power up. the cycle may repeat until the cause of the fault is removed. when the input current, i apd , exceeds 18 ma (typical), the current mirror and biaser attempt to maintain the threshold current by allowing the v apd voltage to fall to a point of equilibrium. in other words, the threshold current represents the compliance of the bias voltage; in this case, the current at which v apd falls 500 mv below its midrange current value. falt asserts, but is not guaranteed to remain asserted, as vapd is pulled down toward ground. if v apd falls below ~3 v, as in the case of a momentary short-circuit or being driven by a programmable current source exceeding the threshold current, bias current generators critical to device operation become satu- rated. this causes falt to deassert and the mirror to shut down. the mirror does not power up until the input current falls below the current limit of the v set amplifier (approximately 2.5 ma), allowing vapd to be pulled up to its normal operating level. the falt pin can be grounded if the logic signal is not used.
ADL5317 rev. 0 | page 11 of 16 applications the ADL5317 is primarily designed for wide dynamic range applications simplifying apd bias circuit architecture. accurate control of the bias voltage across the apd becomes critical to maintain the proper avalanche multiplication factor as the temperature and input power vary. figure 21 shows how to use the ADL5317 with an external temperature sensor to monitor the ambient temperature of the apd. using a look-up table and dac to drive vset, it is possible to apply the correct v apd for the conditions. note that pin 9, pin 10, and pin 12 to pin 15 were removed for simplification. overcurrent protection thermal protection comm falt vset vplv vphv vclh gard vapd i apd ipdm current mirror 5:1 30 v set i apd 5 r 29 r logic supply look-up table and dac temperature sensor 5v optical power translinear log amp apd tia receiver 75v from dc?dc converter data c grd 05456-023 figure 21. typical apd biasing application using the ADL5317 in this application, the ADL5317 is operating in linear mode. the bias voltage to the apd, delivered at pin vapd, is controlled by the voltage (v set ) at pin vset. the bias voltage at vapd is equal to 30 v set . the range of voltages available at vapd for a given high voltage supply is limited to approximately 33 v (or less, for v apd < 41 v). this is because the gard and vapd pins are clamped to within ~40 v below vphv, preventing internal device breakdowns. the input current, i apd , is divided down by a factor of 5 and precisely mirrored to pin ipdm. this interface is optimized for use with any of the analog devices translinear logarithmic amplifiers (for example, the ad8304 or ad8305 ) to offer a precise, wide dynamic range measurement of the optical power incident upon the apd. if a voltage output is preferred at ipdm, a single external resistor to ground is all that is necessary to perform the conversion. voltage compliance at ipdm is limited to v plv or v apd /3, whichever is lower. supply tracking mode some applications for the ADL5317 require a variable dc-to-dc converter or alternative variable biasing sources to supply vphv. for these applications, it is necessary to configure the ADL5317 for supply tracking mode, shown in figure 22 . in this mode, the vset interface is bypassed. however, the full functionality of the precision current mirror remains available. overcurrent protection thermal protection falt vset vplv vphv vphv vclh gard vapd ipdm current mirror 5:1 30 v set r 29 r 5v comm 16 comm 15 comm 14 comm 13 1 2 3 4 5 6 7 8 11 10 9 nc gard variable dc supply 10v to 77v tia 8v to 75v bias across apd data out log rssi 3v to 5.5 v 4v to 6v 05456-024 12 13 nc figure 22. supply tracking mode in supply tracking mode, the v set amplifier is pulled up beyond its linear operating range and effectively placed into a controlled saturation. this is done by applying 3.0 v to 5.5 v at the vset pin. it is also necessary to remove the connection from vclh, which defines the saturation point, to vphv. once the ADL5317 is placed into supply tracking mode, v apd is clamped to 2.0 v below v phv . for those designs where it is desirable to drive vset from the vplv supply, it is necessary to place a 100 k resistor between vset and vplv for v plv > 5.5 v. this is due to input current limitations on the vset pin. translinear log amp interfacing the monitor current output, ipdm, of the ADL5317 is designed to interface directly to an analog devices translinear logarithmic amplifier, such as the ad8304 , ad8305 , or adl5306 . figure 23 shows the basic connections necessary for interfacing the ADL5317 to the ad8305 . in this configuration, the designer is can use the full current mirror range of the ADL5317 for high accuracy power monitoring.
ADL5317 rev. 0 | page 12 of 16 1 2 v set 3 4 11 ipdm 12 nc 10 nc 9 gard 5 v p h v 6 v c l h 7 g a r d 8 v a p d 1 5 c o m m 1 6 c o m m 1 4 c o m m 1 3 c o m m ADL5317 falt vset vplv vphv 0.01 f apd 1nf 1k i apd 0.1 f 0.01 f v p_high 0 v p_low 10k 0 0.01 f 0.1 f tia data path 1 2 3 4 11 scal 12 vout 10 bfin 9 vlog 5 v s u m 6 v n e g 7 v n e g 8 v p o s 1 5 c o m m 1 6 c o m m 1 4 c o m m 1 3 c o m m ad8305 vrdz vref iref inpt i pdm 10na to 1ma ad8305 input compensation network 4.7nf 2k output v out = 0.2 log 10 (i pdm /1na) 0.1 f 200k 3v to 12v 05456-025 1k 1nf 2.5v figure 23. interfacing the ADL5317 to the ad8305 for high accuracy apd power monitoring measured rms noise voltage at the output of the ad8305 vs. input current is shown in figure 24 for the ad8305 by itself and in cascade with the ADL5317. the relatively low noise produced by the ADL5317, combined with the additional noise filtering inherent in the frequency response characteristics of the ad8305 , result in minimal degradation to the noise performance of the ad8305 . 5.5m 0 10n 1m (a) (v rms) 05456-034 5.0m 4.5m 4.0m 3.5m 3.0m 2.5m 2.0m 1.5m 1.0m 0.5m 100n 1 10 100 ad8305 only ad8305 and ADL5317 figure 24. measured rms noise of ad8305 vs. ad8305 cascaded with ADL5317 characterization methods during characterization, the ADL5317 was treated as a high voltage 5:1 precision current mirror. to make accurate measurements throughout the entire current range, calibrated keithley 236 current sources were used to create and measure the test currents. measurements at low current and high voltage are very susceptible to leakage to the ground plane. to minimize leakage on the characterization board, the guard pins are connected to traces that buffer vapd and ipdm from ground. the triax guard connector is also connected to the gard pin of the device to provide buffering along the cabling. figure 25 shows the primary characterization setup. the data gathered is used directly, or with calculation, for all the static measurements, including mirror error between iapd and ipdm , supply tracking offset, incremental gain, and vapd vs. iapd. component selection is very similar to that of the evaluation board, except that triax connectors are used in place of the sma connectors. to measure the pulse response, output noise, and bandwidth measurements, more specialized test setups are used. ADL5317 characterization board falt vphv vplv vset vclh vapd ipdm dc supplies/dmm triax connectors: signal - vapd and ipdm pins guard - guard pin shield - ground keithley 236 keithley 236 05456-026 figure 25. primary characterization setup
ADL5317 rev. 0 | page 13 of 16 dp 8200 dc power supply hp89410a vector signal analyzer + ? + ? + ? vphv vapd vplv vset ipdm ADL5317 + ? + ? + ? + ? + ? 33 f 604 1k 83nf r1 ge 273 ? + +9v fet buffer r l alkaline d cells alkaline d cell alkaline d cells ? + +9v 20k lna ?12v +12v 05456-041 figure 26. configuration for noise spectral density and wideband current noise tds5104 ADL5317 evaluation board vapd falt vphv vplv vset vclh ipdm dc supplies/dmm 1pf r c r c agilent 33250a q1 ad8067 05456-027 figure 27. configuration for pulse response from i apd to i pdm 05456-037 ADL5317 evaluation board vapd falt vphv vplv ipdm vclh vset agilent 33250a r c q1 tds5104 dc supplies/dmm figure 28. configuration for pulse response from v set to v apd network analyzer output r ba power splitter ad8138 eval board ++ ?? ADL5317 eval board vapd vset comm vphv vplv 60v 5v ad8045 1v 50 r f 05456-040 ipdm r f figure 29. configuration for small signal ac response the setup in figure 26 is used to measure the output current noise of the ADL5317. batteries are used in numerous places to minimize introduced noise and remove the uncertainty resulting from the use of multiple dc supplies. in application, properly bypassed dc supplies provide similar results. the load resistor is chosen for each current to maximize signal-to-noise ratio while maintaining measurement system bandwidth (when combined with the low capacitance jfet buffer). the custom lna is used to overcome noise floor limitations in the hp89410a signal analyzer. figure 27 shows the configuration used to measure the i apd pulse response. to create the test current pulse, q1 is used in a common base configuration with the agilent 33250a, generating a negative biased square wave with an amplitude that results in a one decade current step on ipdm. r c is chosen according to what current range is desired. only one cable is used between the agilent 33250a and r c, while everything else is connected with sma connectors. a fet scope probe connects the output of the ad8067 to the tds5104 input. the configuration in figure 28 is used to measure v apd while v set is pulsed. q1 and r c are used to generate the operating current on the vapd pin. an agilent 33250a pulse generator is used on the vset pin to create a 1.6 v to 2.4 v square wave. the capacitance on the gard pin is 2 nf for this test. the setup in figure 29 is used to measure the frequency response from i apd to i pdm . the ad8138 differential op amp delivers a ?1.250 v dc offset to bias the npn transistor and to have a 500 mv drop across r f . this voltage is modulated to a depth of 5% of full scale over frequency. the voltage across r f sets the dc operating point of i apd . r f values are chosen to result in decade changes in i apd . the output current at the ipdm pin is fed into an ad8045 op amp configured to operate as a transimpedance amplifier. the feedback resistor, r f , is the same value as that on the output of the ad8138 . note that any noise at the vset input is amplified by the ADL5317 with a gain of 30. this noise shows up on vapd and causes errors when measuring nanoamp current levels. this noise can be filtered by use of the gard pin. see the gard interface section for more details.
ADL5317 rev. 0 | page 14 of 16 evaluation board table 4. evaluation board configuration options component function default condition vphv, vplv, gnd high and low voltage supply and ground pins. not applicable vset apd bias voltage setting pin. the dc voltage applied to vset determines the apd bias voltage at vapd. v apd = 30 v set . not applicable r11, c8 apd input compensation. provides essential high frequency compensation at the vapd input pin. c8 = 1 nf (size 0603) r11 = 1 k (size 0603) vapd, l1, c9 input interface. the evaluation board is config ured to accept an input current at the sma connector labeled vapd. filtering of this current can be done using l1 and c9. l1 = 0 (size 0805) c9 = open (size 0805) ipdm, r1 mirror interface. the output current at the sma connector labeled ipdm is 1/5 the value at vapd. r1 allows a resistor to be installed for applications where a scaled voltage referenced to i apd instead of a current is desirable. r1 = open (size 1206) r7, r8, r9, r10, c6, c7, c10 guard options. by populating r9 and/or r10, the shell of the vapd sma connector is set to the gard potential. r7 and r8 are installed so that the guard potential can be driven by an external source, such as the vsum potential of the analog devices optical log amps. c7 filters noise from the vset interface and provides a high frequency ac path to ground. additional filtering is possible by installing a capacitor at c10. c10 should equal c7. r7 = r8 = 0 (size 0402) r9 = r10 = open (size 0402) c7 = 0.01 f (size 0805) c6 = c10 = open (size 0402) vplv, w1, w2, r3 optional supply tracking mode. connecting jumper w2 and opening jumper w1 places the ADL5317 into supply tracking mode. in this mode, the voltage at vapd is typically 2 v below v phv . r3 = 100 k for v plv > 5.5 v. r3 = 0 (size 0402) w1 = open w2 = closed vclh, w1, c4, r6 extended linear operating range. closing w1 connects pin vphv and pin vclh. this allows for an extended linear control range of v apd using v set . w1 = closed c4 = open (size 0805) r6 = 0 (size 0402) falt, r2 falt interface. r2 is a resistive pull-up that is us ed to create the logic signal at falt. r2 = 10 k (size 0603) c1, c2, c3, c5, r4, r5 supply filtering/decoupling. c1 = c2 = 0.01 f (size 0402) c3 = 0.1 f (size 0603) c5 = 0.1 f (size 1206) r4 = r5 = 0 (size 0402)
ADL5317 rev. 0 | page 15 of 16 1 2 3 4 11 ipdm 12 nc 10 nc 9 gard 5 v p h v 6 v c l h 7 g a r d 8 v a p d 1 5 c o m m 1 6 c o m m 1 4 c o m m 1 3 c o m m ADL5317 falt vset vplv vphv c7 0.01 f c10 open c8 1nf r11 1k c9 open l1 0 vapd r1 open ipdm output r8 0 r7 0 c6 open r9 open r3 0 w2 r2 10k r10 open vphv r5 0 c5 0.1 f c2 0.01 f c3 0.1 f r4 0 falt vset v plv r6 0 w1 c4 open c1 0.01 f gnd 05456-030 figure 30. ADL5317 evaluation board schematic 05456-031 figure 31. ADL5317 evaluation board layout 05456-032 figure 32. ADL5317 evaluation board silkscreen
ADL5317 preliminary technical data rev. 0 | page 16 of 16 outline dimensions 1 0.50 bsc 0.60 max p i n 1 i n d i c a t o r 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicato r 0.90 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 3.00 bsc sq * 1.65 1.50 sq 1.35 16 5 13 8 9 12 4 exposed pad (bottom view) * compliant to jedec standards mo-220-veed-2 except for exposed pad dimension. figure 33. 16-lead lead frame chip scale package [lfcsp_vq] 3 mm x 3 mm body, very thin quad (cp-16-3) dimensions shown in millimeters ordering guide model temperature range package description package option branding ADL5317acpz-reel7 1 C40c to +85c 16-lead lead frame chip scale package (lfcsp_vq) cp-16-3 r00 ADL5317acpz-wp 1 C40c to +85c 16-lead lead frame chip scale package (lfcsp_vq) cp-16-3 r00 ADL5317-eval evaluation board r00 1 z = pb-free part. ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05456-0-7/05(0)

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